1. Field of the Invention
The invention relates to, for example, a clamp circuit used for a television signal superimposing circuit to superimpose a television signal (composite video signal) and a signal (composite video signal) from a microcomputer. In particular, it relates to a clamp circuit which is available when a part of a clamp pulse for the composite video signal drops out. Furthermore, if explaining in detail, the invention relates to a clamp circuit which operates with the same function as that of a pedestal clamp circuit when the clamp pulse is inputted and operates with the same function as that of a sync tip clamp circuit when the clamp pulse is not inputted (including the case when the pulse drops out).
2. Description of the Prior Art
In processing a composite video signal, since mean electrical potential changes by the information of a composite video signal, in particular, an intensity signal (contrast), clamp processing is performed to make direct current electrical potential constant by using the clamp circuit. Generally there arc two categories in this clamp processing. One of them is a sync tip clamp processing which keeps the sync tip (leading edge of a sink portion) level to a constant direct current electrical potential (sync tip direct current "DC" electrical potential). The other is a pedestal clamp processing which keeps a pedestal level of the composite video signal to a constant direct current electrical potential (pedestal direct current "DC" electrical potential).
First, before explaining these two categories of the clamp processing, the sync tip DC electrical potential and the pedestal DC electrical potential will be explained using FIG. 9A and FIG. 9B. FIG. 9A and FIG. 9B show timing relationship of a composite video signal and a clamp pulse. FIG. 9A shows the composite video signal which includes at least a horizontal synchronizing pulse period, a pedestal period (including a color burst), and a video signal period (which is the portion shown by zig-zag line) per one horizontal period.
Minimum electrical potential of the composite video signal is, as shown by mark A, a portion which is a part of horizontal synchronizing pulse, or a portion called a sink. The direct current electrical potential of the sync tip level is called a sync tip DC electrical potential. On the other hand, a central direct current level shown by mark B is a pedestal level whose direct current electrical potential is called a pedestal DC electrical potential. FIG. 9B shows a clamp pulse. The clamp pulse generated at the portion for clamping the composite video signal is generally used to detect the pedestal DC electrical potential.
The sync tip clamp processing is explained below. The processing is generally used in such a circuit as to keep the leading edge of the sink constant by using a peak hold circuit. For example, it may be constructed by the circuit shown in FIG. 10. In FIG. 10, the circuit comprises an NPN transistor (Tr1) 27, a direct current (DC) bias source 28, whose electrical potential is Vsync, a hold capacitor (C1) 29 and a discharge resistor (R1) 30.
The sync tip clamp circuit constructed as described above operates as follows. When the sync tip DC electrical potential of the composite video signal inputted into the input terminal is lower than Vsync (a direct current electrical potential from the DC bias source 28)-Vbe (which is the voltage between base-emitter of the transistor 27, approximately 0.7 V), the transistor 27 is conductive state, therefore it rapidly charges the hold capacitor 29. During the period of the sync tip in the composite video signal, or horizontal synchronizing pulse period, the sync tip DC electrical potential of the composite video signal in an output terminal becomes [Vsync-Vbe] and the charge continues until the transistor 27 becomes non-conductive state. Accordingly, the sync tip DC electrical potential becomes [Vsync-Vbc], and the composite video signal based on the electrical potential is outputted from the output terminal.
On the other hand, since the transistor 27 is non-conductive state when the sync tip DC electrical potential of the composite video signal inputted into an input terminal is higher than [Vsync-Vbe], the charge of the capacitor 29 is discharged until the sync tip DC electrical potential becomes [Vsync-Vbe] by the resistor 30. Accordingly, the sync tip DC electrical potential becomes [Vsync-Vbe], and the composite video signal based on the electrical potential is outputted from the output terminal. As described above, the sync tip DC electrical potential is converged to a constant electrical potential [Vsync-Vbe] and the composite video signal based on the constant electrical potential [Vsync-Vbe] is outputted from the output terminal. A circuit using diodes may be used instead of the transistor 27.
Next, the pedestal clamp processing is explained below. In the processing, the circuit receives a clamp pulse during the pedestal period of a composite video signal to monitor the direct current electrical potential of the composite video signal during the pulse period of the clamp pulse, and keeps the monitored electrical potential constant. For example, the prior pedestal processing circuit is shown in FIG. 11.
In FIG. 11, the pedestal processing circuit comprises a current mirror circuit 31 constructed by a pair of PNP transistors, a differential pair transistor 32 constructed by a pair of NPN transistors, a reference voltage resource 33 for generating a reference electrical potential Vped of the clamp, and a constant electric current source 34. The above mentioned current mirror circuit 31, the differential pair transistor 32, and the constant electric current source 34 constitute a comparator. The pedestal processing circuit further comprises a differential pair transistor 35 constructed by a pair of PNP transistors, a constant current source 36, and a current mirror 37 constructed by a pair of NPN transistors. The above mentioned differential pair transistor 35, the constant current source 36 and the current mirror 37 constitute a differential amplification circuit. The pedestal processing circuit further comprises a DC bias source 38, a resistor 39, a sample hold capacitor 40, and an emitter follower transistor 41 constructed by an NPN transistor.
The comparator which is constructed by the current mirror circuit 31, the differential pair transistor 32, and the constant current source 34 detects the potential difference of the pedestal DC electrical potential of the composite video signal inputted into an input and the reference electrical potential Vped of the reference voltage source 33. The comparator includes a switch 16, which activates/deactivates the operation of the comparator by ON/OFF operation thereof. In other words, only when a clamp pulse inputted into the switch 16 is of high level (pulse period), the switch 16 turns ON and the comparator becomes active state.
When the switch 16 is ON in response to the clamp pulse, the comparator compares the pedestal DC electrical potential of the composite video signal inputted with the reference electrical potential Vped of the reference voltage source 33, charges/discharges the capacitor 40 based on the result obtained by comparison, and holds the electrical potential of the capacitor 40 to an electrical potential based on the reference electrical potential Vped. On the other hand, when the switch 16 is OFF without receiving a clamp pulse, the comparator is in non-active state. In other words, since the comparator does not operate, the electrical potential of the capacitor 40 is held as it is.
Also, the differential amplification circuit constructed by the differential pair transistor 35, the constant current source 36 and the current mirror 37 controls the electric current flowing into the resistor 39 by the electrical potential charged in the capacitor 40, which controls the direct current electrical potential appearing at the output terminal. Now, if the pedestal DC electrical potential of the composite video signal inputted through the input terminal and the emitter follower transistor 41 is higher than the reference electrical potential Vped, the capacitor 40 discharges, and the electrical potential of the capacitor 40 falls. Therefore, the electrical potential of the capacitor 40 becomes lower than the reference electrical potential of the DC bias source 38, so the current mirror 37 of the differential amplification circuit pulls the current through the resistor 39. As a result, the pedestal DC electrical potential of the output terminal falls.
On the other hand, if the pedestal DC electrical potential of the composite video signal inputted through the input terminal and the emitter follower transistor 41 is lower than the reference electrical potential Vped, the capacitor 40 is charged, and the current mirror 37 of the differential amplification circuit supplies the electrical current through the resistor 39, so that the pedestal DC electrical potential of the output terminal rises. As a result of feedback operation like this, the pedestal DC electrical potential of the composite video signal in the output terminal coincides with the reference electrical potential Vped, so that the composite video signal based on the reference electrical potential Vped is outputted from the output terminal.
Accordingly, in sync tip clamp processing, a clamp pulses is not required, which can simplify the system for processing a composite video signal. But, if the composite video signal is the one which has been transmitted like a television signal, shrinkage and elongation of the sink occur according to good or bad transfer condition and various kinds of the signal processing circuits. In other words, the potential difference between the sync tip DC electrical potential and the pedestal DC electrical potential of the composite video signal inputted may become small or large, which may change the pedestal DC electrical potential. As a result, the position such as the pedestal representing the bright and dark may shift from the original position.
On the other hand, in a pedestal clamp processing, since the pedestal DC electrical potential is clamped, failure will not occur at the position of the pedestal as long as a clamp pulse is outputted precisely. But, since a clamp pulse is needed necessarily in a pedestal clamp processing, accuracy decreases when dropping of a clamp pulse occurs. The pedestal clamp processing can not be applied to the system having the mode of processing a composite video signal without the clamp pulse.